ChipStack
UVMAgent
Teams enhance UVM testbenches & coverage efficiently, reduce cycles
ChipStack UVMAgent enables design and verification engineers to intelligently update and extend existing UVM environments without requiring deep UVM architecture expertise. The agent creates comprehensive test plans, implements targeted functional coverage, and performs sophisticated testbench enhancements.
Once the testbench updates are accepted, the engineer runs their commercial simulator externally and then returns to the agent to track coverage and provide suggested bug fixes that can be approved and automatically implemented.
Set up and completion time is cut from weeks to days. The agent enables both verification engineers and RTL designers to efficiently enhance existing UVM environments, catching bugs earlier while maintaining reusable, scalable verification infrastructure.
UVM Workflow Enhancements
ChipStack UVMAgent transforms UVM workflows from specialized, time-intensive efforts into guided, highly automated processes. By rapidly updating existing verification environments for evolving RTL designs while giving engineers control over each step, the agent enables comprehensive verification that dramatically accelerates development schedules.
1
UVM Test Plan creation
UVMAgent begins by analyzing the "mental model" created by ChipStack MentalModelAgent from design specifications.
With this comprehensive understanding of design intent, it builds sophisticated UVM test plans that capture verification scenarios across multiple abstraction levels. The generated test plan focuses on design features, including performance, stress, security, and other key UVM test categories.
Designers and verification engineers can tune the test plan, such as controlling randomization, checkers, and verbosity.
2
Functional Coverage Creation
UVMAgent analyzes the mental model to automatically create comprehensive functional coverage models using SystemVerilog covergroups. The system identifies critical design behaviors, edge cases, and interaction scenarios that traditional code coverage might miss.
The agent creates coverpoints for key design features, cross-coverage for feature interactions, and temporal coverage for protocol sequences. Engineers can refine coverage models using natural language, with the system automatically implementing the corresponding covergroup enhancements and sampling strategies.
Designers who understand edge cases best can now contribute functional coverage insights without mastering covergroup syntax, ensuring early visibility into verification completeness.
ChipStack UVMAgent runs these functional covergroups in the target simulator, and then suggests reachable/unreachable covers.
3
UVM Testbench Creation or Update
UVMAgent analyzes current testbench architecture and automatically generates sophisticated UVM testbenches or testbench updates -- intelligently extending existing verification environments. This saves weeks of manual SystemVerilog development.
The UVMAgent can generate various UVM components or updates based on natural language inputs, such as:
Driver updates to support new interface requirements & timing constraints
Agent configuration updates to support new design features & protocols
Scoreboard enhancements for improved checking & reference model integration
Sequence library extensions with new stimulus patterns & constrained random scenarios
The UVMAgent shows exactly what changes will be made before implementation, maintaining verification environment integrity.
4
Run Simulator in Native Environment
Once testbench enhancements are accepted, design verification engineers can use them to run their simulator in its native environment.
5
Coverage Gap Analysis & Reporting
After the simulation run is complete, UVMAgent automatically analyzes functional coverage results and identifies verification gaps using the previously defined coverage models and covergroups. The system provides detailed reports showing:
Line, toggle, & functional coverage holes
Coverage gap hints
Suggested waivers
Recommended testbench stimulus enhancements
Engineers can refine coverage models using natural language, with the agent automatically implementing enhanced stimulus generation to close coverage gaps.
6
Debug guidance with automatic code update option
If a test fails, UVMAgent provides automated debug analysis with specific bug fix suggestions. The system provides input on:
Triage for the failure
Likely error root cause(s)
Bug classification
Recommended RTL or testbench changes
If the engineer approves the suggested bug fixes, ChipStack UVMAgent can automatically implement the RTL code and/or testbench changes while maintaining UVM testbench compatibility. The engineer can then rerun the simulator to verify that the changes are correct.