Empowers designers to simulate RTL early, reducing iterations
ChipStack UnitSimAgent enables designers to perform unit-level simulation without requiring deep SystemVerilog knowledge. The agent first creates a test plan and testbench. Once the testbench is accepted, the unit simulation agent will run the commercial simulator and provide suggested bug fixes that can be approved and automatically implemented.
Set up and completion time is cut from weeks to only hours. The agent can be used directly by RTL designers, allowing them to catch bugs immediately and deliver higher-quality RTL to verification teams.
End-to-End Unit Simulation Workflow
ChipStack UnitSimAgent transforms unit-level simulation from a verification specialist activity into an accessible task for RTL designers. By automating the simulation workflow while giving designers control over each step, the agent enables shift-left verification that compresses development schedules.
1
Test Plan creation
UnitSimAgent begins the process by analyzing the "mental model" that was created by ChipStack MentalModelAgent from early design RTL, even when a design specification is unavailable.
With this clearly articulated understanding of design intent, the agent builds a comprehensive simulation test plan that captures the bulk of the verification scenarios on the first pass. Designers can use natural language queries to identify and fill verification holes, with the agent systematically generating and updating verification objectives and test scenarios.
2
Testbench creation
UnitSimAgent produces SystemVerilog testbenches that implement the verification objectives defined in the test plan.
The agent generates comprehensive test cases, stimulus patterns, and response checking logic while creating simulation-ready environments with minimal designer input. The system handles unit-level stimulus generation including directed test sequences, boundary condition testing, and single-block functional verification.
Designers then refine the testbench by using natural language to identify missing scenarios, and the UnitSimAgent automatically generates the corresponding test cases, stimulus patterns, and checkers.
3
Push-button simulation execution
Once the testbench is accepted, designers can run their selected simulation tools with seamless, single-button execution. Cadence Xcelium and Synopsys VCS are already integrated with and configured for ChipStack UnitSimAgent.
4
Debug guidance with automatic TB update option
When tests fail, the UnitSimAgent provides automated debug analysis with specific fix suggestions. The system offers guided debugging for test failures while handling simulation tool integration and file management transparently. The agent provides input on:
Triage for the failure
Likely error root cause(s)
Bug classification
RTL and/or testbench change suggestions
If the engineer approves the suggested bug fix, ChipStack UnitSimAgent can automatically implement the testbench code change -- then rerun the simulator to verify corrections.
