Establishes design intent context for functional verification.
ChipStack MentalModelAgent takes the early RTL design and specification and uses advanced AI technology to create a "mental model" reflecting design intent, capturing functional behavior, interface protocols, and boundary conditions. Engineers can use natural language to tune the mental model.
The mental model serves as a comprehensive, contextual foundation for ChipStack's verification AI agents FormalAgent, UnitSimAgent, and UVMAgent. It also improves and accelerates the verification team's understanding of the RTL.
Mental model
Microarchitecture map of design intent
Effective verification begins with a clear articulation of design intent. ChipStack’s LLM-based assistants can expand concise design outlines into structured specifications that define functional behavior, interface protocols, and boundary conditions. This comprehensive specification minimizes ambiguities and provides a definitive reference for later verification activities.
The system generates a living microarchitecture map of the design intent that evolves with the RTL and serves every discipline involved in ASIC development.
This comprehensive document includes block overviews, detailed functionality descriptions, interface protocols, port and parameter definitions, and implementation details, such as:
Complete specifications for communication interfaces and data transfer protocols multimodal inputs, interpreting both textual specifications and visual diagrams such as hand-drawn state machines, block diagrams, and architectural visuals:
Representative transaction flows and system performance benchmarks
Comprehensive parameter definitions, custom data types, and timing domain architecture
Traffic arbitration and quality-of-service policies, diagnostic features, control status registers, and additional design elements