ChipStack
FormalAgent
Slashes formal verification project time from weeks to days.
ChipStack FormalAgent enables engineers to dramatically accelerate the formal verification process. First, they use agentic AI to build the formal verification test plan and SVA testbench, with engineers refining each element using natural language interfaces.
Once the engineer accepts the testbench, ChipStack’s formal verification AI agent will run the specified commercial formal verification tool and provide pass/fail results. For any failed tests, FormalAgent will suggest bug fixes for review that can be approved and then automatically implemented.
End-to-End Formal Verification Automation
ChipStack FormalAgent transforms formal verification from a specialist-only methodology into an accessible tool for design and verification engineers. By automating the formal verification workflow, while still giving engineers control over each step, the agent eliminates traditional barriers to formal verification adoption.
1
Test Plan Creation
FormalAgent begins the process by analyzing the “mental model” that was created by ChipStack MentalModelAgent from early design RTL, with or without a design specification available.
With this clearly articulated understanding of design intent, the agent builds a comprehensive formal test plan that captures the bulk of the verification scenarios on the first pass. Engineers can use natural language queries to identify and fill coverage gaps, with the system generating assertion, assumption, and cover scenarios systematically.
2
Testbench Creation
FormalAgent produces SystemVerilog assertions, cover properties, and assumptions alongside the necessary Tcl scripts with proper file integration. The agent handles VIP integration and complex protocol verification while creating production-ready testbenches. Engineers then refine the testbench by using natural language to specify additional operational states, constraint scenarios, and/or modify assertion properties within the testbench implementation.
3
Push-button formal verification execution
Once the testbench is accepted, designers can run their formal verification tools with seamless, single-button execution. Cadence Jasper and Synopsys VC Formal are already integrated with and configured for ChipStack FormalAgent.
4
Debug guidance with automatic testbench update option
When tests fail, the FormalAgent provides automated debug analysis with specific fix suggestions. The system offers guided debugging for test failures and coverage gaps while handling tool integration complexity transparently.
If the engineer approves the suggested bug fix, ChipStack FormalAgent can automatically implement the testbench code change -- then rerun the formal verification tool to verify corrections.
